1. Technical Field
The present disclosure relates to electrically erasable and programmable memories.
The present disclosure more particularly relates to an electrically erasable and programmable memory, comprising memory cells arranged in bit lines and word lines.
2. Description of the Related Art
FIG. 1 shows an example of EEPROM memory 1 of the aforementioned type. The memory comprises memory cells CEikj connected to word line selection lines WLSLi and bit lines BLkj transverse to the word lines. The bit lines are gathered into columns COLk comprising M bit lines BLk0, . . . BLkj . . . , BLkM-1. The memory cells connected to a same selection line WLSLi form a word line WLi. The memory cells of a same word line WLi connected to the M bit lines of a column COLk form a memory word W1ik allowing M bits to be stored. For the sake of simplicity, only one word W1ik belonging to a column COLk and a word line WLi is shown in FIG. 1.
Each memory cell CEikj comprises a floating gate transistor FGT and an access transistor AT of MOS type. The transistor AT comprises a gate terminal G connected to the line WLSLi, a drain terminal D connected to a bit line BLkj and a source terminal S connected to a drain terminal D of the transistor FGT. The transistor FGT comprises a control gate terminal G connected to a gate control line CGLk and a source terminal S connected to a source line SL. The line SL is connected to the ground through a transistor SLT driven by a signal SLS. The line CGLk is linked to a column selection line CLk through a gate control transistor CGTk having a gate terminal connected to the line WLSLi.
Each line WLSLi is controlled by a signal VWL supplied by an output OUTi of a line decoder RDEC1. Each line CLk is controlled by a gate control signal VCG supplied by a column latch LT1k. Each latch LT1k is controlled by a column selection signal SCOLk supplied by an output OUTk of a column decoder CDEC. The decoders RDEC1 and CDEC respectively receive the most significant bits ADH and the least significant bits ADL of the address of a word W1ik to be selected in the memory 1.
Each bit line BLkj is linked to a bit line latch LP1kj driven by the column selection signal SCOLk. Each latch LP1kj is connected to a bus WB to receive, before a program operation, a data bit bj among M bits b0 to bM-1 of a data word to be written. Each bit line BLkj is also linked to a sense amplifier SAj through a column selection transistor TSk, a read transistor TR and a multiplex bus MB. The transistors TSk are driven by the column selection signal SCOLk while the transistors TR are driven by a read signal READ. Sense amplifiers SA0 to SAM-1, connected in input to the bus MB and in output to a bus RB, allow the M bits of a word W1ik to be read.
In such a memory, an operation for erasing or programming memory cells consist in injecting or extracting electric charges by tunnel effect (Fowler Nordheim effect) in the floating gates of the transistors FGT. A transistor FGT has in the programmed state, a threshold voltage VTw, and in the erased state, a threshold voltage VTe. When a read voltage Vread comprised between VTw and VTe is applied to the control gate thereof, a transistor FGT in the programmed state is conductive, which corresponds by convention to a logic “1”, and a transistor in the erased state is blocked, which corresponds by convention to a logic “0”; an inverse convention may be adopted.
Collectively erasing the transistors FGT of a word line WLi is made by applying a voltage Vpp of 15 to 20 V to the control gates of the transistors FGT, while the source line SL is at 0 and the bit lines BLkj are at a floating potential. Individually programming the transistors FGT is obtained by applying the voltage Vpp to the drains of the transistors FGT through the access transistors AT, while the control gates of the transistors FGT are at 0 and the source line SL is at a floating potential. These operations are made using the decoders RDEC1, CDEC, latches LT1k and LP1kj, by increasing the supply voltage of these elements, from Vcc of around 1.8 to 5.5 V, to the voltage Vpp. The voltage Vpp is generated by a charge pump PMP from the supply voltage Vcc of the memory.
Table 1 below sums up the values of the control signals during the operations for erasing, programming and reading a memory cell CEikj. In Table 1, Vs is a control signal present on the source line SL, VBL is a control signal present on the bit line BLkj and Vsense is a signal supplied by the sense amplifiers SAj.
TABLE 1OperationControl signalsERASINGPROGRAMMINGREADINGVCGVpp0 (ground)VreadVWLVppVppVccVs0 (ground)Floating0 (ground)VBLFloatingVppVsense
Due to the application of the voltage Vpp to the gates or drains thereof, several transistors are subjected to a not negligible electrical stress during the successive erase/program cycles. They are in particular the access transistors AT, the floating gate transistors FGT, transistors in the column LT1k and line bit LP1kj latches, and transistors in the line decoder RDEC1.
The gate oxides of these transistors are chosen consequently, and are made to support voltages that may reach 30 V. However, gate oxides are not perfect and have several drawbacks or impurities susceptible of causing breakdown in normal use conditions. Thus, the breakdown of a transistor is sometimes observed far before the specified hundreds of erase/program cycles. Although there is little prospect of a transistor breakdown, the number of memory cells present in an EEPROM memory is high and, statistically, the failure rate of a memory due to a gate oxide breakdown is one of the main causes, even the main cause of failure of an EEPROM memory being used.
To compensate for this drawback, it is known, during the manufacturing tests, to apply to memories an electrical stress which may be greater than that to which a memory in normal use is subjected. These operations allow the memories having manufacturing defects or very insufficient robustness to be eliminated. However, these operations require several thousand program cycles to test all the transistors and therefore eliminate the memories having gate oxide defects. These operations prove to be insufficient since EEPROM memories are usually designed to support 1 million program cycles by byte, and that the failure rate of such a memory due to a gate oxide breakdown still reaches a ratio of around one memory out of 1 million (1 ppm).
It has also been suggested to associate to data bits stored in the memory an error correction code, or ECC code, allowing at least one erroneous bit to be detected and corrected in a bit string. For example, a 4-bit hamming code added to 8 bits of data allow an erroneous bit to be detected and corrected when reading the bit string. This precaution usually proves to be sufficient to correct the consequences of the breakdown of a floating gate transistor FGT, but is not effective to counter a failure of an access transistor AT. Indeed, it may be impossible to properly erase the memory cells of a word line WLi connected to a faulty access transistor AT, or to properly program memory cells of a bit line BLkj connected to a faulty access transistor.
The patent FR 2 826 496 (U.S. Pat. No. 6,934,192) describes adjustments of an EEPROM memory to avoid the breakdown effects of an access transistor during phases for erasing cells of a word line connected to a faulty access transistor, and during phases for programming cells of the bit line connected to the faulty access transistor.
The patent FR 2 858 725 (U.S. Pat. No. 7,239,192) describes a charge pump associated to a circuit allowing a failure to be detected in stages of the charge pump, the charge pump comprising a replacement stage provided to replace a corrupted stage. It is also provided to associate to each memory word an error correction code allowing some cases of bit reading errors to be corrected.
However, these solutions do not allow the effects of transistor gate oxide breakdown to be avoided in an EEPROM memory, if the faulty transistor is located in a bit line or column latch, or in the word line decoder. More generally, these solutions do not make it possible, in all the aforementioned cases, to detect that a bit stored in the memory is erroneous due to a gate oxide breakdown, nor to correct the value of an erroneous bit. Indeed, if the breakdown of a gate oxide concerns for example a transistor of the line decoder, all the memory cells of a word line may be faulty. The result is that the provision of an error correction code memorized in memory cells of the same word line is ineffective.
In some equipment comprising EEPROM memories, like vehicle-borne equipment, the failure rate must be very low. It is therefore desirable to reduce the failure rate of EEPROM memories resulting from transistor gate oxide breakdowns.